View LVT162245_340011.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

74LVT162245 * 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25: Series Resistors in A Port Outputs
January 1999 Revised June 2005
74LVT162245 * 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25: Series Resistors in A Port Outputs
General Description
The LVT162245 and LVTH162245 contains sixteen noninverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The LVT162245 and LVTH162245 are designed with equivalent 25: series resistance in both the HIGH and LOW states on the A Port outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The LVTH162245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These non-inverting transceivers are designed for low voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT162245 and LVTH162245 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pullup resistors to hold unused inputs (74LVTH162245), also available without bushold feature (74LVT162245). s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s A Port outputs include equivalent series resistance of 25: making external termination resistors unnecessary and reducing overshoot and undershoot s A Port outputs source/sink r12 mA. B Port outputs source/sink 32 mA/64 mA s Functionally compatible with the 74 series 162245 s Latch-up performance exceeds 500 mA s ESD performance:
Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V
s Also packaged in plastic Fine Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number 74LVT162245G (Note 1)(Note 2) 74LVT162245MEA (Note 2) 74LVT162245MTD (Note 2) 74LVTH162245G (Note 1)(Note 2) 74LVTH162245MEA 74LVTH162245MEX 74LVTH162245MTD 74LVTH162245MTX Package Number BGA54A (Preliminary) MS48A MTD48 BGA54A MS48A MS48A MTD48 MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBE] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBE] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL]
Note 1: Ordering code "G" indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2005 Fairchild Semiconductor Corporation
DS012446
www.fairchildsemi.com
74LVT162245 * 74LVTH162245
Logic Symbol
Connection Diagrams
Pin Assignments for SSOP and TSSOP
Pin Descriptions
Pin Names OEn T/Rn A0-A15 B0-B15 NC Description Output Enable Input (Active LOW) Transmit/Receive Input Side A Inputs/3-STATE Outputs Side B Inputs/3-STATE Outputs No Connect
FBGA Pin Assignments
1 A B C D E F G H J B0 B2 B4 B6 B8 B10 B12 B14 B15 2 NC B1 B3 B5 B7 B9 B11 B13 NC 3 T/R1 NC VCC GND GND GND VCC NC T/R2 4 OE1 NC VCC GND GND GND VCC NC OE2 5 NC A1 A3 A5 A7 A9 A11 A13 NC 6 A0 A2 A4 A6 A8 A10 A12 A14 A15
Truth Tables
Inputs OE1 Pin Assignment for FBGA L L H T/R1 L H X Outputs Bus B0-B7 Data to Bus A0-A7 Bus A0-A7 Data to Bus B0-B7 HIGH-Z State on A0-A7, B0-B7
Inputs OE2 L L H T/R2 L H X Outputs Bus B8-B15 Data to Bus A8-A15 Bus A8-A15 Data to Bus B8-B15 HIGH-Z State on A8-A15, B8-B15
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance
(Top Thru View)
www.fairchildsemi.com
2
74LVT162245 * 74LVTH162245
Functional Description
The LVT162245 and LVTH162245 contain sixteen noninverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation.
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
www.fairchildsemi.com
74LVT162245 * 74LVTH162245
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 4) VI GND VO GND VO ! VCC VO ! VCC Output at HIGH State Output at LOW State V mA mA mA mA mA
0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 50 50
64 128
r64 r128 65 to 150
qC
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH-Level Output Current LOW-Level Output Current Free Air Operating Temperature Input Edge Rate, VIN 0.8V-2.0V, VCC 3.0V B Port A Port B Port A Port Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA
32 12
64 12
40
0
85
10
qC
ns/V
't/'V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage A Port VCC (V) 2.7 2.7-3.6 2.7-3.6 3.0 2.7-3.6 2.7 3.0 3.0 2.7 2.7 B Port 3.0 3.0 3.0 II(HOLD) (Note 5) II(OD) (Note 5) II Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF Power Off Leakage Current Bushold Input Minimum Drive 3.0 3.0 3.6 3.6 3.6 0 75 2.0 VCC0.2 2.4 2.0 0.8 0.2 0.5 0.4 0.5 0.55 V 2.0 0.8 TA
40qC to 85qC
Max
Min
Units V V V V V V V V II
Conditions
1.2
18 mA
VO d 0.1V or VO t VCC 0.1V IOH IOH IOH IOH IOL IOL IOL IOL IOL IOL VI VI
12 mA 100 PA 8 mA 32 mA
12 mA 100 PA 24 mA 16 mA 32 mA 64 mA 0.8V 2.0V
B Port VOL Output LOW Voltage A Port
75
500
PA PA
10
(Note 6) (Note 7) VI 5.5V 0V or VCC 0V VCC VI VI VI
500 r1 5
1
PA
r100
PA
0V d VI or VO d 5.5V
www.fairchildsemi.com
4
74LVT162245 * 74LVTH162245
DC Electrical Characteristics
Symbol IPU/PD IOZL IOZL (Note 5) IOZH IOZH (Note 5) IOZH ICCH ICCL ICCZ ICCZ 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current (Note 8)
Note 5: Applies to Bushold versions only (74LVTH162245).
(Continued)
VCC (V) TA
Parameter Power Up/Down 3-STATE Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current
40qC to 85qC
Max
Units
Conditions VO VI VO VO VO VO 0.5V to 3.0V GND to VCC 0.5V 0.0V 3.0V 3.6V
Min
0-1.5V 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6
r100 5 5
5 5 10 0.19 5 0.19 0.19 0.2
PA PA PA PA PA PA
mA mA mA mA mA
VCC V O d 5.5V Outputs HIGH Outputs LOW Outputs Disabled VCC d V O d 5.5V, Outputs Disabled One Input at VCC 0.6V Other Inputs at VCC or GND
'ICC
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3
(Note 9)
TA 25qC Typ 0.8 Max Units V V CL Conditions 50 pF, RL (Note 10) (Note 10) 500:
Min
0.8
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW.
5
www.fairchildsemi.com
74LVT162245 * 74LVTH162245
AC Electrical Characteristics
TA Symbol Parameter VCC Min tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tOSHL tOSLH tOSHL tOSLH A Port Output to Output Skew (Note 11) B Port Output to Output Skew (Note 11) Output Disable Time for B Port Output Output Disable Time for A Port Output Output Enable Time for B Port Output Output Enable Time for A Port Output Propagation Delay Data to B Port Output Propagation Delay Data to A Port Output 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.5 1.5 1.5 1.5 CL 3.3V r 0.3V Max 4.0 3.7 3.5 3.5 5.3 5.6 4.6 5.3 5.6 5.5 5.4 5.1 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.5 1.5 1.5 1.5
40qC to 85qC
50 pF, RL 500: VCC Min 2.7V Max 4.6 4.1 3.9 3.9 6.3 7.2 5.4 6.9 6.3 5.5 6.1 5.4 1.0 1.0 ns ns ns ns ns ns ns ns Units
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance
Symbol CIN CI/O
(Note 12)
Parameter Conditions VCC VCC 0V, VI 0V or VCC 0V or VCC 3.0V, VO Typical 4 8 Units pF pF
Input Capacitance Input/Output Capacitance
Note 12: Capacitance is measured at frequency f
1 MHz, per MIL-STD-883, Method 3012.
www.fairchildsemi.com
6
74LVT162245 * 74LVTH162245
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A
7
www.fairchildsemi.com
74LVT162245 * 74LVTH162245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
www.fairchildsemi.com
8
74LVT162245 * 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25: Series Resistors in A Port Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
www.fairchildsemi.com

▲Up To Search▲

Price & Availability of LVT162245

	To Download LVT162245 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .